The invention relates to semiconductor testing, and more particularly, to optimizing test time for automatic test equipment.
Modern semiconductor products pack powerful functionality into miniscule packages. As semiconductor components become more complex, physical integrated circuits shrink, and manufacturing rates increase, the need for accurate and rapid testing of the circuits sharpens. Although testing of semiconductors, especially new products, is crucial to maintain quality control, testing slows the overall productivity of the manufacturing process and adds complexity and cost to an already very complex and expensive process.
Automatic test equipment (ATE) performs most modern testing of semiconductors during the engineering and production processes. The ATE receives a collection of components, often provided on a single wafer, as a batch of packaged integrated chip components, as a circuit board, or as a system, and automatically provides input signals to the various components and measures the components"" output responses. With the ever-increasing complexity of semiconductors and other electronics products, however, ATE is increasingly complex as well. Accordingly, ATE represents a large investment that requires regular upgrading and replacement as new technology surpasses the capabilities of older ATE.
To maximize the value of an ATE, semiconductor manufacturers make every effort to improve the efficiency of the ATE while maintaining testing accuracy. Even minor improvements in the test time for each individual circuit tested may incrementally save significant sums by improving the throughput of the ATE, thus reducing the overall cost per component.
Methods and apparatus for statistical process control of test according to various aspects of the present invention provide improved test times at run-time by optimizing the wait period between applying input signals and collecting output test signal data. In one embodiment, a tester identifies one or more acceptable systems, circuit boards, or components and performs testing to establish baseline test data. The systems, circuit boards, or components are then tested using a series of different waiting periods to generate wait time optimization data. The wait time optimization data and the baseline data are then statistically analyzed, for example using statistical process control techniques, to identify a wait period for which the test process is out of control. An optimized wait period is then selected that is suitable to maintain the test process under control.